The present invention relates to a semiconductor integrated circuit used for a DC-DC converter of a switching regulator system and a method for operating the same, and in particular relates to a technique effective in reducing a switching loss by reducing a deviation from the operational principle of zero-volt switching (ZVS).
For battery powered electronic devices such as a notebook PC (Personal Computer), a DC-DC converter is used for converting a DC voltage supplied from an AC adapter or a battery into a DC voltage supplied to a load that is a central processing unit of a notebook PC (CPU), namely, a microprocessor.
In recent years, as a countermeasure against global environmental problems, energy saving has been emphasized and an attention has been paid on an increase in efficiency and a reduction in power consumption, in particular a reduction in standby power consumption, of a switching power supply used for various electronic devices.
Conventionally, in a DC-DC converter, a high conversion efficiency is achieved by using a switching regulator performing a PWM (Pulse Width Modulation) control, a PFM (Pulse Frequency Modulation) control, or the like. That is, the DC-DC converter of a switching regulator system controls the on/off of a semiconductor switch by feedback control so as to maintain a DC voltage supplied to a load at a predetermined target value.
The following FIG. 31 of Japanese Patent Laid-Open No. 2000-197348 (Patent Document 1) and the disclosure related thereto describe a voltage-mode-type DC-DC converter including an error amplifier, a comparator, a triangular waveform generation circuit, a driver circuit, a high-side switch element, a low-side switch element, an inductor, and a capacitor.
A reference voltage is supplied to a non-inverting input terminal of the error amplifier, and an output voltage at a connection node between the inductor and the capacitor is supplied to an inverting input terminal of the error amplifier. An output voltage of the error amplifier is supplied to a non-inverting input terminal of the comparator, a triangular waveform signal generated from the triangular waveform generation circuit is supplied to an inverting input terminal of the comparator, and an output signal of the comparator is supplied to the driver circuit. Since the driver circuit complementarily drives the high-side switch element and the low-side switch element, an on-off operation of the high-side switch element is opposite to an on-off operation of the low-side switch element.
The following Japanese Patent Laid-Open No. 2001-016083 (Patent Document 2) describes that in a switching semiconductor device, such as a transistor or a field effect transistor, one such element cannot strike a balance between an increase in switching speed (speed of switching between an on-state and an off-state) and a reduction in on-resistance (saturation voltage) because the switching speed and the on-resistance are generally in a trade-off relationship. The following Patent Document 2 describes that in order to reduce a power loss, a first transistor having a high switching speed and a second transistor having a low on-resistance are coupled in parallel, and thus a conductive state and non-conductive state of a conduction path are switched by using both the first and the second transistors. At the time of switching from a non-conductive state to a conductive state, first, the first transistor having a high switching speed is turned on, and then at the timing when this element is saturated, the second transistor having a low on-resistance is turned on, and at the time of switching from a conductive state to a non-conductive state, the first transistor is turned off after turning-off of the second transistor. Furthermore, FIG. 17 of Patent Document 2 and the disclosure related thereto describe that the first transistor, the second transistor, and a controller are formed in a first region 64a, a second region 64b, and a third region 64c of a semiconductor chip, respectively.
Japanese Patent Laid-Open No. 2004-040854 (Patent Document 3) describes that in a chopper type switching power supply, a first transistor having a small current capacity and a second transistor having a large current capacity are coupled in parallel on a power supply path. Here, the first transistor having a small current capacity is controlled to be in an off-state by delaying the first transistor relative to the second transistor having a large current capacity. Thus, in the course of switching, a source to drain voltage of a MOS transistor is maintained at zero and a power loss in a switch element is suppressed.